An Area Efficient High speed VLSI Architecture for Scalable InPlace Computation of Real valued FFT

Authors

  • SadiqVali Syed Author

Keywords:

Fast Fourier transform computation in-place

Abstract

Real value is gained quickly. Physical signals may be simulated using Fourier transforms, 
which is attracting researchers' attention. In FFT, memory access conflicts and high throughput are 
among the most difficult problems to solve.' As a result, incorporating imaginary values is 
superfluous in all real-valued applications. Besides taking up extra space, it also slows down 
operations. Because the storage unit contains all of the internal processes, this is a good thing. For 
all the fictitious computations, it takes up a lot of memory space. The best potential method to 
eliminate memory conflicts and increase current performance is hence RFFT. With more stages and 
more internal computations, RFFT of Largerbitwidth requires more twiddle factor computations. 
Using a smaller bitwidth instead of a bigger bitwidth, we were able to improve area and delay while 
avoiding memory conflicts.

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Published

26-03-2022

How to Cite

An Area Efficient High speed VLSI Architecture for Scalable InPlace Computation of Real valued FFT. (2022). Indo-American Journal of Pharma and Bio Sciences, 20(1), 1-10. https://iajpb.org/index.php/iajpb/article/view/99