Efficient Multiple Error Correction by Using Two Bit Overlap Codes

Abstract

Error-correction codes are a common way to guard against data corruption. OLS codes 
frequently make use of linear block codes with single- and double-error correction. Orthogonal Latin 
square (OLS) codes are a type of one-step majority-logic-decodable (OS-MLD) error correcting codes. 
Decoding these codes is quick and simple because to the use of short codes. Soft faults in 
semiconductor memories, OLS codes are used to rectify multiple cell failures. Reconfigurable designs 
like field programmable gate arrays can benefit from OLS codes generated from Latin squares 
(FPGA). By adopting Latin Square codes, this work describes the parity regulation matrices and the 
strategy for lowering the decoding block by enlarging the original OLS code. This work describes the
implementation of orthogonal Latin square codes by their parity control matrices and the method of 
lowering the decoding block by enlarging the real size of the OLS code. The generalization problem is 
addressed in this study by narrowing the scope of the suggested technique to only include codes 
with improved errorcorrection.